Load line, Q-point, optimum Q-point,bias stabilization, stability factor

Load line, Q-point , optimum Q-point, bias stabilization, stability factor:

Stability factor:

The stability factor gives the constant value of collector current (\(I_C\)) against the variation of leakage current (\(I_{CBO}\)) with temperature . The higher the value of stability factor less will be the stability of Q-point. The stability factor increases with increases temperature and vice-versa.

The stability factor is defined as the rate of change of collector current(\(I_C\)) with leakage current (\(I_{CBO}\))when both \(\beta \) and \(V_{BE}\)( input voltage )are hold constant i.e.

Stability factor(s)=\(\frac{dI_C}{dI_{CBO}}\)

As we know that in CE-configuration, the output collector current is given by,

$$I_C=\beta I_B+(1+\beta)I_{CBO}$$Where \(I_{CBO}=I_{CO}\)=leakage current

Differentiate both side with respect to \(I_C\),

$$\frac{dI_C}{dI_C}=\beta \frac{dI_B}{dI_C}+(1+\beta)\frac{dI_{CBO}}{dI_C}$$

$$1=\beta \frac{dI_B}{dI_C}+(1+\beta)\frac{1}{\frac{dI_C}{dI_{CBO}}}$$

$$1=\beta \frac{dI_B}{dI_C}+(1+\beta)\frac{1}{s}$$

$$(1+\beta)\frac{1}{s}=1-\beta {dI_B}{dI_C}$$

$$s=\frac{(1+\beta)}{1-\beta \frac{dI_B}{dI_C}}$$This is the required expression for stability factor.

• In CB mode:

We have the expression for collector current as,

$$I_C=\alpha I_E+I_{CBO}$$

Differentiating with respect \(I_C\)

$$\frac{dI_C}{dI_C}=\alpha \frac{dI_E}{dI_C}+\frac{dI_{CBO}}{dI_C}$$

$$1=\frac{1}{\frac{dI_C}{dI_{CEO}}}$$

$$1=\frac{1}{s}$$

$$\therefore s=1$$

• In CE mode:

We have,$$I_C=\beta I_B+(1+\beta) I_{CBO}$$

Differentiating with respect to\(I_C\),

$$\frac{dI_C}{dI_C}=\beta \frac{dI_B}{dI_C}+(1+\beta)\frac {dI_{CBO}}{dI_C}$$

$$1=0+(1+\beta)\frac{1}{\frac{dI_C}{dI_{CBO}}}$$

$$1=(1+\beta)\frac{1}{s}$$

$$s=1+\beta $$

$$\therefore s=1+\beta$$This means the collector current changes 101 times as that of leakage current(\(I_{CBO}\)).

• In CC mode:

  

In this circuit,

$$V_{CC}=I_ER_C+I_BR_B+V_{BE}$$

$$V_{CC}+(I_B+I_C)R_C+I_BR_B+V_{BE}$$

$$V_{CC}=I_BR_C+I_CR_C+I_BR_B+V_{BE}$$

$$V_{CC}-V_{BE}=I_B(R_B+R_C)+I_CR_C$$

$$I_B=\frac{V_{CC}-V_{BE}-I_CR_C}{R_B+R_S}$$

Now, differentiate with respect to \(I_C\)

$$\frac{dI_B}{dI_C}=\frac{-RC}{R_B+R_C} \frac{dI_C}{dI_C}$$

$$\frac{dI_B}{dI_C}=\frac{-R_C}{R_B+R_C}$$Now, substituting the value of \(frac{dI_B}{dI_C}\) in the expression of stability factor,

$$s=\frac{1+\beta}{1-\beta \biggl(\frac{dI_B}{dI_C}\biggr)}$$

$$s=\frac{1+\beta}{1-\beta \biggl(\frac{-R_C}{R_B+R_C}\biggr)}$$

$$s=\frac{(1+\beta)(R_B+R_C)}{(1+\beta)R_C+R_B}$$

DC load line ,Q-point or optimum point:

The line joining the saturation point and cut off point for dc biasing of transistor is called dc load line.

The line AB shown in the figure above represents the dc load line. The points lying in between points A and B in the dc load line forms active region. In the figure above, the points C, D, E, lie in the active region. In this region the transistor is functionable . In this case BE junction is forward biased and CE junction is reverses biased.

The mid-point of the line joining the cut-off points and saturation point is called the optimum Q-point or Q-points because at this point the transistor can give maximum possible output or the point on the dc load line which corresponds the value of \(I_C\)and \(V_{CE}\) that exist in transistor when no input signal is applied is Q-point.

Poiints of Q-points and maximum undistorted output

The point of Q-point has direct impact on the output of the transistor as shown in the figure .

Case 1:

If Q-point, \(Q_1\) is near to cut off point as in figure. Then thecut of fpoint clips the output voltage to \(A_1\), which is called cut off clipping. Here, maximum positive swing=\(I_{CQ}R_{ac}\) . It is called the cut off clipping because positive swing of the signal drives the transistor to cutoff.

Case 2:

If Q-point, \(Q_1\) is near saturation point in a figure, then the saturation point clips the output voltage to \(B_2\) and this is called saturation clipping. Here, the maximum positive swing=\(V_{CEO}\).

Case 3:

If Q-point, \(Q_3\) is at the mid-point of cutoff and saturation point, then the maximum possible output is obtained as shown in figure. So, this point is called optimum point or Q-point transistors.

Hence, to get the optimum point of transistors we should take the value of \(R_C\) such that the voltage drop across \(R_C\) is just half of the supplied voltage(\(V_{CE}\)).

Here, maximum undistorted signal =2\(V_{CEQ}\)

References:

(1)Theraja, B.L. Basic Electronics. N.p.: S.Chand, n.d. Print.

(2)C.L.Arora. Refresher Course in Physics. Vol. II and III. N.p.: S.Chand, 2006. Print.

(3)Malvino. Electronic Principles. N.p.: Tata McGraw-Hill, n.d. Print.

(4)N.Nelkon and P.Parker. Advanced Level Physics. 5th ed. N.p.: Arnold Heinemann, n.d. Print.

(5)Priti Bhakta Adhikari,Diya Nidhi Chaatkuli, Ishowr Prasad Koirala. A Textbook of Physics (2nd Year). N.p.: Sukunda Pustak Bhawan, 2070. Print.