FET as amplifier and UJT as relaxation oscillator

FET as amplifier and UJT as relaxation oscillator:

FET as amplifier:

The common source terminal JFET as amplifier circuit is as shown in figure in which the input signal is give to the gate terminal through coupling capacitor \(C_1\) and output is taken across \(R_l\) which is connected to drain terminal.

The ac equivalent circuit of figure is shown in below figure,

1. Input impedance:

   The input impedance of circuit is given by,

$$Z_{in}=R_G\parallel R_{GS}$$ Where,\(R_G=R_1\parallel R_2\)

\(R_{GS}\) is gate to source resistance and its value is infinity because the gate current \(I_g\)=0 but practically \(R_{GS}\) is infinitely large. So,

$$Z_{in}\sim R_G=R_1\parallel R_2$$This input impedance is very high.

2.Output impedance

It is given by

$$Z_{out}=R_D\parallel r_d$$Where \(r_d\) is drain load resistance and

\(r_d\)=AC drain resistance

3.Voltage gain

The ratio of output to input voltage is called gain, i.e.

$$A_v=\frac{V_{out}}{V_{in}}/dotsm(1)$$In our case,

$$V=V_{in}$$

$$V_{out}=i_dZ_{out}$$

Since,

$$i_d=-g_m\times V_{in}$$

$$g_{in}=\frac{1}{R_D}$$

$$V_{out}=-g_m V_{in}(R_D\parallel r_d)$$

$$A_v=/frac{-g_m V_{in}(R_D\parallel r_d)}{V_{in}}$$

$$A_v=-g_m(R_D\parallel r_d)$$

Since,\(r_d>>R_D\) we have,

$$A_v=-g_m R_D$$

Working

When the positive going input signal is given to the gate terminal, it decreases value of gate (\(V_{GS}\)) source voltage. The decreasing value of \(V_{GS}\), increase the channel width by decreasing the depletion layer. As a result, the resistance across output section decreases. As a result the drop across drain resistor \(R_B\) increases. This finally decreases output across load resistor. This means positive going half cycle of input signal gives negative going output signal. This means phase reversal in JFET amplifier.

For point wise

When negative half cycle of input ac is applied then,

• The reverse biasing to gate is increased.
• Then the depletion layer of gate to channel is widened.
• So, the drain resistance is increased.
• Then the drain current (\(I_D\)) is decreased.
• The drop across \(R_D\) (i.e.\(I_DR_D\)) also decreased.
• Consequently \(V_{DS}=V_{DD}-I_DR_D\), will be increased. This means the negative going signal produces the position going output signal. So, the phase of output with respect to input is reversed.

UJT as relaxation oscillator:

The circuit diagram below shows the RC network of resistor \(R_1\) and capacitor C used for charging the capacitor. This figure is the relaxation oscillator using UJT. When the battery \(V_{BB}\) is switch on, the capacitor gets charged through \(R_1\). It charges vigorously i.e. exponentially until peak voltage (\(V_c\)) is reached.

At this condition, UJT switches to low resistance, conducting mode and the capacitor discharges between E and \(B_1\). As (\(V_c\)) capacitor voltage fails to zero, UJT gets switched off. This is reverse biased condition of UJT. Then, next cycle begins. As a result, output is obtained in the form of toothed wave as shown in figure.

Other application of FET:

1) FETs are commonly used as input amplifiers in devices such as oscilloscope, voltmeters, and other measuring devices due to their high input impedance.

2) FETs are used in RF amplifiers for FM devices.

3) FET is a voltage controlled device, so it is used as voltage-variable resistors in operational amplifier.

4) FETs posses low intermodulation distortions. So they are used in mixer circuits.

References:

(1)Theraja, B.L. Basic Electronics. N.p.: S.Chand, n.d. Print.

(2)C.L.Arora. Refresher Course in Physics. Vol. II and III. N.p.: S.Chand, 2006. Print.

(3)Malvino. Electronic Principles. N.p.: Tata McGraw-Hill, n.d. Print.

(4)N.Nelkon and P.Parker. Advanced Level Physics. 5th ed. N.p.: Arnold Heinemann, n.d. Print.

(5)Priti Bhakta Adhikari,Diya Nidhi Chaatkuli, Ishowr Prasad Koirala. A Textbook of Physics (2nd Year). N.p.: Sukunda Pustak Bhawan, 2070. Print.

5) FETs find their applications in low frequency amplifiers due to its small coupling capacitors.